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| TUESDAY, June 8, 2004, 4:30 PM - 6:30 PM | Room: 6A | ||
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TOPIC AREA: POWER | ||
| SESSION 11 | |||
| Power Grid Design and Analysis Techniques | |||
| Chair: Eli Chiprout - Intel Corp., Chandler, AZ | |||
| Organizers: Abhijit Dharchoudhury, Lei He | |||
| This session deals with power grid and clock design and analysis. The first paper considers buffer sizing for low power with clock skew constraints. The second paper discusses optimal placement of power pads and pins. The third paper proposes a stochastic approach to P/G analysis and the fourth paper describes a practical application of macro-modeling to P/G analysis. The last paper presents a layout decompaction technique to correct EM failures. | |||
 11.1 |
Buffer Sizing for Clock Power Minimization Subject to General Skew Constraints |
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| Speaker(s): | Kai Wang - Univ. of California at Santa Barbara, Goleta, CA | ||
| Author(s): | Kai Wang - Univ. of California at Santa Barbara, Goleta, CA Malgorzata Marek-Sadowska - Univ. of California, Santa Barbara, CA | ||
| 11.2 | Optimal Placement of Power Supply Pads and Pins | ||
| Speaker(s): | Min Zhao - Freescale Semiconductor, Inc., Austin, TX | ||
| Author(s): | Min Zhao - Motorola, Inc., Austin, TX Yuhong Fu - Motorola, Inc., Austin, TX Vladimir Zolotov - Motorola, Inc., Austin, TX Savithri Sundareswaran - Motorola, Inc., Austin, TX Rajendran Panda - Motorola, Inc., Austin, TX | ||
| 11.3 | A Stochastic Approach to Power Grid Analysis | ||
| Speaker(s): | Sanjay Pant - Univ. of Michigan, Ann Arbor, MI | ||
| Author(s): | Sanjay Pant - Univ. of Michigan, Ann Arbor, MI David Blaauw - Univ. of Michigan, Ann Arbor, MI Vladimir Zolotov - Motorola, Inc., Austin, TX Savithri Sundareswaran - Motorola, Inc., Austin, TX Rajendran Panda - Motorola, Inc., Austin, TX | ||
| 11.4s | Efficient Power/Ground Network Analysis for Power Integrity-Driven Design Methodology | ||
| Speaker(s): | Su-Wei Wu - Elan Microelectronics Corp., Hsinchu, Taiwan | ||
| Author(s): | Su-Wei Wu - Elan Microelectronics Corp., Hsinchu, Taiwan Yao Wen Chang - National Taiwan Univ., Taipei, Taiwan | ||
| 11.5s | Reliability-Driven Layout Decompaction for Electromigration Failure Avoidance in Complex Mixed-Signal IC-Designs | ||
| Speaker(s): | Goeran Jerke - Robert Bosch GmbH, Reutlingen, Germany | ||
| Author(s): | Goeran Jerke - Robert Bosch GmbH, Reutlingen, Germany Jens Lienig - Dresden Univ. of Tech., Dresden, Germany Juergen Scheible - Robert Bosch GmbH, Reutlingen, Germany | ||
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